FIT2069 Computer architecture - Semester 1, 2015

This unit covers the internal mechanism of computers and how they are organised and programmed. Topics include combinatorial and sequential logic, Boolean Algebra, Karnaugh maps, counters, ripple adders, tree adders, memory/addressing, busses, speed, DMA, data representation, machine arithmetic, microprogramming, caches and cache architectures, virtual memory and translation look-aside buffers, vectored interrupts, polled interrupts, pipelined architecture, superscalar architecture, data dependency, hazards, CISC, RISC, VLIW machine architectures.

Mode of Delivery

Workload Requirements

Minimum total expected workload equals 12 hours per week comprising:

(a.) Contact hours for on-campus students:

• Two hours of lectures
• One 3-hour laboratory or one 2-hour tutorial (alternating weeks)

(b.) Additional requirements (all students):

• A minimum of 7-8 hours independent study per week for preparing for and completing lab and project work, private study and revision.

See also Unit timetable information

Additional workload requirements

This is a technically oriented unit where content in any given week depends strongly on content in preceding weeks. Therefore students should plan and commit the minimum specified hours for personal study every week. Laboratory work will require preparation before attendance.

The unit content requires a strong focus on understanding content through the semester.

Unit Relationships

Prerequisites

FIT1031 or FIT1001 and FIT1008 or FIT1015

Chief Examiner

Campus Lecturer

Your feedback to Us

Previous Student Evaluations of this Unit

In response to the last SETU of this unit, the following changes have been made:

• Additional examples of real world hardware will be added into the lecture slides;
• Additional supplementary reading will be added;

Student feedback has highlighted the following strength(s) in this unit:

• "I really liked how cohesive all the topics in this unit were. 10/10 unit."
• "Interesting subject matter, well structured and clearly refined over the years. Labs are challenging and useful. Having no assignments is great and makes sense in this unit."
• "The content is introduced at a proper pace and each lecture builds on the previous one so the students don't feel overwhelmed by having to absorb a large amount of information in one go."
• "The practicals were interesting and relevant The lectures were interesting and well explained. Good use of real world examples in lectures"

Academic Overview

Learning Outcomes

• combinatorial and sequential logic, Boolean Algebra, Karnaugh maps, and hazards;
• counters, ripple adders, tree adders, memory/addressing, computer busses, logic and bus speed, and Direct Memory Access;
• data representation for integers and floating point operands;
• machine arithmetic, microprogramming;
• storage hierarchies, caches and cache architectures, performance impact of caching;
• virtual memory and translation look-aside buffers, performance impact of TLB caching;
• vectored and polled interrupt handling;
• pipelined architecture, superscalar architecture, data dependency, and hazards;
• CISC, RISC, VLIW machine architectures.

• model combinatorial and sequential logic circuits using a simulator tool;
• perform programming tasks in assembly code.

Unit Schedule

*Unit Schedule details will be maintained and communicated to you via your learning system.

Teaching Approach

• Lecture and tutorials or problem classes
  This teaching and learning approach provides facilitated learning, practical exploration and peer learning.
• Laboratory-based classes
  This teaching approach is practical learning.

Assessment Summary

Examination (3 hours): 60%; In-semester assessment: 40%

Assessment Requirements

Assessment Policy

Assessment Tasks

Participation

There are 6 Tutorial Exercises each worth 1.667% of the total mark (assessed).

There are 6 Laboratory Exercises each worth 5% of the total mark (assessed, preparation required).

Tutorials and Laboratories are scheduled in alternating weeks.

Attendance is expected and strongly recommended.  This unit is tightly integrated so if students miss a Tutorial or Laboratory they will have difficulty understanding later material.

• Assessment task 1

  Title:

  Laboratory Exercises

  Description:

  6 Laboratory Exercises. Individual assessment per task. Preparation required.
  
  Attendance is expected and strongly recommended.  This unit is tightly integrated so if students miss a Laboratory they will have difficulty understanding later material.

  Weighting:

  Total 30% (5% each)

  Criteria for assessment:

  The criteria used to assess laboratory tasks are:

  1. All programs must assemble and execute correctly. Evidence of testing is required.
  2. Programs must meet the problem specification.
  3. Assembly code should be readable and maintainable.
  4. Programs should be documented.
  5. All algorithms should follow the style presented in laboratory examples and be correct.
  6. Logic simulator circuits must comply with the specified truth table or other functional definition.

  Due date:

  Weeks 2, 4, 6, 8, 10 and 12

• Assessment task 2

  Title:

  Tutorial Exercises

  Description:

  6 Tutorial Exercises. Individual assessment per task.
  
  Attendance is expected and strongly recommended.  This unit is tightly integrated so if students miss a Tutorial they will have difficulty understanding later material.

  Weighting:

  Total 10% (1.667% each)

  Criteria for assessment:

  The criteria used to assess submissions are:

  1. Correctness and understanding - there may be more than one "right" answer in many cases. We will look for answers that reflect understanding of the underlying principles and theories.
  2. Completeness - that you have answered all parts of each question.
  3. Presentation - that you have presented your answers in a suitably formatted style.
  4. Use of evidence and argument - you are able to explain your position by using logical argument drawing on the theory presented in the unit.

  Due date:

  Weeks 1, 3, 5, 7, 9 and 11

Examinations

• Examination 1

  Weighting:

  60%

  Length:

  3 hours

  Type (open/closed book):

  Closed book

  Electronic devices allowed in the exam:

  Non-programmable scientific calculators will be permitted.

Learning resources

Feedback to you

• Informal feedback on progress in labs/tutes
• Test results and feedback

Extensions and penalties

Returning assignments

Assignment submission

Online submission

If Electronic Submission has been approved for your unit, please submit your work via the learning system for this unit, which you can access via links in the my.monash portal.

Recommended Resources

Software:

Logisim software (free)

Xspim/Spim software (free)

Supplementary Reading:

http://www.csse.monash.edu.au/~carlo/SYSTEMS/

Recommended text(s)

William Stallings. (). Computer Organization and Architecture: Designing for Performance. (8th Edition) Prentice Hall (ISBN: 13: 9780136073734).

Morris Mano and Charles Kime. (). Logic and Computer Design Fundamentals. (4th Edition) Pearson Prentice Hall (ISBN: 0-13-140539-X).

Examination material or equipment

Non-programmable scientific calculators will be permitted.

Other Information

Policies

Graduate Attributes Policy

Student Charter

Student services

Monash University Library

Disability Liaison Unit

Other

Engineers Australia Stage 1 competencies

This unit is a core unit in the Bachelor of Software Engineering accredited by Engineers Australia. Engineers Australia Accreditation Policy of Professional Engineering Programs requires that programs demonstrate how engineering graduates are prepared for entry to the profession and achieve Stage 1 competencies. The following information describes how this unit contributes to the development of these competencies for the Bachelor of Software Engineering. (Note: not all competencies may be emphasised in this unit).

Relationship between Unit Learning Outcomes and BSE Course Outcomes

Relationship between Unit Learning Outcomes and Assessments